Do not assume MLCC by default
The load can be a capacitor, IC, connector branch or downstream subsystem. Thermal localization must identify the actual heating element.
IPHONE PMIC / MAIN-RAIL / POWER-SEQUENCE FORENSICS
Power the board.
Power the board.
Then trace the first rail that fails.
Separate battery feed, VDD_MAIN, always-on rails, clock/reset, AP multi-phase bucks, DRAM/NAND rails and PMU latch behavior before injecting, splitting a board or replacing the PMIC.
PMIC STARTUP EVIDENCE CHAIN
BATT
MAIN
AON
BUCKS
CLOCK
RESET
Current draw is only one clue. The strongest diagnosis combines rail presence, timing, load behavior, known-good comparison and the exact boot stage.
01 — PMIC STARTUP SEQUENCE
Trace eight stages from battery feed to SoC boot
Select a power domain to narrow the rail database and diagnostic interpretation.
02 — POWER FAILURE PROFILER
Hard short, false short, AON dropout, reset collapse and load droop
V2 separates direct observation from likely cause and requires proof before component removal.
SELECTED FAILURE
Observed evidence
Competing domains
Proof required
03 — INJECTION SAFETY MATRIX
Rail identity comes before voltage injection
The source contains useful ceiling references, but V2 treats them as page references—not permission to inject automatically.
| Rail Family | Source Operating Range | Source Ceiling | Primary Risk | V2 Rule |
|---|---|---|---|---|
| PP_VDD_MAIN / VDD_BOOST | 3.8–4.3V | 3.8V source ceiling | Feeding sensitive branches / excessive heating | Confirm exact shorted rail, isolate battery/charger path, start well below nominal and current-limit. |
| PP_CPU_CORE / GPU_CORE | ~0.7–0.95V | 0.90V source ceiling | Permanent AP damage from over-voltage | Low resistance can be normal. Never apply main-rail voltage to core rails. |
| PP1V8_AON | ~1.8V | 1.8V source ceiling | Back-feeding PMU / always-on logic | Prefer resistance/isolation first; inject only after topology and max voltage are confirmed. |
| DRAM / memory rails | ~1.1V class | 1.15V source ceiling | Memory/AP damage | Do not treat low Ω as a short without exact-model known-good comparison. |
| Clock / crystal nodes | Bias / AC waveform | DO NOT INJECT | Oscillator / SoC damage | Use oscilloscope, not voltage injection. |
Injection is a localization technique after rail identification—not a generic first diagnostic step. Current limit, board temperature and exact voltage ceiling matter.
04 — MASTER POWER RAIL DATABASE
Voltage + GR + resistance + injection guidance
Source-derived references are preserved as bench references. Exact-model schematic/boardview and known-good measurements take precedence.
| Domain | Rail / Signal | Source Voltage | Source GR | Resistance | Source Injection Guidance | Interpretation |
|---|
05 — LIVE POWER-RAIL EVALUATOR
One measurement narrows the stage—not the component
Dynamic rail behavior, boot timing and exact-model reference remain essential.
06 — SOURCE RULES CORRECTED
Do not let one rail reading force a PMIC repair
V2 keeps the useful source structure while downgrading unsupported one-to-one conclusions.
Not automatically PMIC failure
Confirm PMIC input, rail short, enable/state, interposer connection and load before replacing the PMIC.
Not automatically PMIC BGA
Clock, AP execution, reset logic, power-hold state, interposer and rail collapse can all produce similar current behavior.
Low resistance can be normal
Core rails are inherently low impedance. Exact-model known-good comparison and source-current behavior are mandatory.
Not automatically buck coil / MLCC
Capture actual VCORE droop, battery/main-rail sag and thermal state under the failing workload.
Does not prove sequencing health
A rail can be correct at idle yet fail during ramp, clock/reset transition or high-current load.
07 — PMIC / POWER CASE DOSSIER
Record rail timing, current signature and isolation evidence
Preserve exact model, power source, current curve, rail values, injection conditions and thermal result.