Top-board standalone evidence
If a supported model can boot or progress farther with one layer separated, that is useful isolation evidence. It does not automatically prove every circuit on that layer is healthy.
Combine DC current shape with power rails, clock/reset, NAND access, USB state and panic/restore evidence. No single amp reading should be treated as a final component diagnosis.
Source V1 organizes the sequence from main battery/system rails through always-on, key/clock, AP bucks, NAND and I²C/OS stages.
Board construction, connector routing, PMIC generations and normal low-resistance rails change by iPhone family. Use exact boardview/schematic data whenever available.
Click each stage to inspect source-derived rails, expected behavior and the safer interpretation of a missing stage.
The seven source signatures are preserved, but V2 converts each into a probability branch with explicit confirmation tests.
Values are retained as uploaded-source references. Exact model/board known-good data should take precedence.
| Stage | Rail / Signal | Operating Voltage | GR / Diode | Resistance to GND | Signal Type | What Abnormal Supports |
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V2 explicitly distinguishes hard short, low reading, open circuit and voltage dropout from the final failed component.
The engine ranks fault domains from combined evidence. It intentionally avoids one-number component verdicts.
Record the measurements that justified the repair and the measurements that confirmed it afterwards.
The source includes useful split-board ideas, but V2 removes universal temperature and “100% healthy” claims.
If a supported model can boot or progress farther with one layer separated, that is useful isolation evidence. It does not automatically prove every circuit on that layer is healthy.
Measure the short on each separated layer and identify which side still carries the abnormal load before thermal injection or component removal.
Very low resistance can be normal on high-current core rails. Never inject main-rail voltage into a CPU-core rail; use the exact rail voltage/current limit appropriate to the board.
Restore failure plus NAND-rail collapse supports a storage-power branch. Error percentage alone should not be used as a universal NAND diagnosis.
The source contains several direct one-to-one mappings. V2 keeps them as source hypotheses unless supported by a confirming measurement.
Check storage power, clocks, USB mode and restore behavior before NAND rework.
Use exact restore logs and board measurements; do not map one error number to one component universally.
Use the exact panic string to identify the missing sensor or bus before replacing the charging flex by assumption.
Check panic/restore/storage/I²C and board-layer evidence before sandwich rework.